This invention relates generally to insulated gate field effect transistors (IGFETs) such as MOSFET devices and integrated circuits, and more particularly the invention is directed to such devices and integrated circuits which can operate at an ultra-low voltage of 0.6 volt or less.
During the past few years, demand for high performance and low power digital systems has grown very rapidly. Several factors have contributed to this fast growth. First, laptop and notebook computers, and personal communication systems have gained popularity. Consequently, portable applications that traditionally required a modest performance (such as wrist watches and calculators) are now dominated by devices that demand a very high performance. The demand for portability of these new systems limits their weight and size, placing a severe constraint on their power dissipation. Second, speed, density and size of non-portable CMOS based systems have increased tremendously in recent years. Thus, power consumption, which was not a concern in these systems, now is becoming a critical parameter.
The main approach for reducing power has relied on power supply scaling. This is due to the fact that in CMOS digital circuits delivered power is proportional to the square of power supply voltage. Since power supply reduction below three times the threshold voltage (3V.sub.t) will degrade circuit speed significantly, scaling of power supply should be accompanied by threshold voltage reduction. However, the lower limit for threshold voltage is set by the amount of off-state leakage current that can be tolerated (due to standby power consideration in static circuits, and avoidance of failure in dynamic circuits and memory arrays). It is seen that if regular MOSFETs are used, a lower bound for power supply voltage becomes inevitable.
Silicon-on-insulator (SOI) technology offers much promise for ultra large scale integrated circuits using sub-micron gate technology.. This technology employs a layer of semiconductor material overlying an insulation layer on a supporting bulk wafer. The structure can be formed by a number of well-known techniques, such as zone melting and recrystallization (ZMR), separation by implanted oxygen (SIMOX), and Bonded and Etchback (BESOI). Typically, the structure comprises a film of monocrystalline silicon on a buried layer of silicon oxide in a monocrystalline silicon substrate.
The bulk silicon material in which the channel of a MOSFET device is formed is typically grounded or connected to the source region of the device. However, in SOI MOSFETs the monocrystalline silicon film is often unbiased or floating. Heretofore, a SOI MOSFET has been operated as a lateral bipolar transistor by connecting the silicon film to the gate and exploiting the extra current produced by the device. However, this operation requires the body voltage to be larger than 0.6 volt. And since the current gain of the bipolar device is small, the extra drain (collector) current comes at the cost of excessive input (base) current, which contributes to standby current. This is contrary to a low-power operation.